This invention relates to insulated-gate field-effect-transistor (IGFET) circuits and more particularly to IGFET circuits of the type which employ a string of transistors connected in series between two terminals of the circuit.
Many well-known and widely used IGFET circuits such as multiple-input NAND gates and serial decoders require the use of a series string of two or more transistors connected in series between an output terminal and a power supply terminal. Each transistor in the string has a gate electrode connected to receive an input signal and a conduction channel connected in series with that of the other transistors in the string. When all the transistors in the string are driven to the "ON" state by appropriate input signals, the output terminal is "pulled" towards the voltage on the power supply terminal. One problem with circuits using a string of transistors is that when the number of transistors in the string is greater than two, the time required for the output terminal to reach its final voltage after all the transistors in the string are switched to the "ON" state becomes excessive for many applications requiring high switching speeds. The switching delay of such circuits depends on the time required for the load capacitance at the output terminal and the parasitic capacitances at the source/drain junctures of the transistors in the string to discharge (charge) through respective discharge (charge) paths formed by the conduction channels of the transistors in the string. Although, the conduction channel resistance of an IGFET in the "ON" state is relatively very small compared to that of an IGFET in the "OFF" state, the combined "ON" state channel resistances of several transistors connected in series is sufficient to produce excessive discharge (charge) times for the load and parasitic capacitances.
A commonly used technique for reducing the switching delay in a circuit using a string of transistors is to reduce the "ON" state channel resistance of the transistors in the string by uniformly increasing their conduction channel widths. Although this technique reduces switching delay in those applications where the load capacitance on the output terminal of the circuit is much greater than the parasitic capacitances at the source/drain junctures in the string, the technique is deficient in many applications where the load capacitance is on the same order of magnitude as the parasitic capacitances. In the latter applications a uniform increase in the widths of the transistors of the string results in little or no reduction in the switching delay.
Another known technique for reducing the switching delay in a circuit using a long string of transistors is to provide additional circuitry in parallel with the string for rapidly discharging the load capacitance in response to a predetermined voltage drop across a portion of the string. This latter technique has the deficiency of requiring additional circuitry for its implementation and, consequently, of increasing the manufacturing cost of a circuit which uses the technique.
Therefore, a need exists for apparatus which reduces the switching delay in an IGFET circuit having a string of more than two transistors which is suitable for those applications where the load capacitance on the circuit is of the same order of magnitude as the parasitic capacitance at a source/drain juncture in the string and which does not require additional circuitry.